(1) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device having a polycide structure for electrodes or interconnects.
(2) Description of the Related Art
In the field of silicon semiconductor integrated circuits, application of metal silicide films whose resistivity is low and melting point is high is diversified. For example, in the DRAM (Dynamic Random Access Memory) used nowadays, the interconnects for memory cell portions such as gate electrodes (word interconnects) of a transistor and bit interconnects require the films having low resistance and high melting point due to the scaling down of the widths of interconnects necessitated by design rules. Accordingly, metal silicide films are widely used for the gate electrodes, the bit interconnects, etc.
Also, the characteristic of the recent metal silicide interconnect is that, in most cases, it is in the form of a polycide structure in which the entire surface or a part of the metal silicide film is in contact with a silicon film containing impurities, and the metal silicide film and the silicon film constitute a layered structure (polycide structure).
Sequential steps of a method for fabricating a prior art semiconductor device of the kind to which the present invention relates are shown in FIGS. 1A-1D.
As shown in FIG. 1A, a surface of a silicon substrate 1 is thermally oxidized by a local oxidation process (LOCOS) whereby a field oxide film 2 of 0.3 .mu.m thick is formed so as to define an element formation region. Then, after a gate oxide film 3 of 10 nm thick is formed by thermally oxidizing a surface of the silicon substrate at the element formation region, a phosphorus (P) doped silicon film 4 of 0.1 .mu.m thick and a tungsten silicide film 5 of 0.1 .mu.m are sequentially deposited and stacked on the entire surface. On the resulting entire surface, phosphorus ions are implanted at an acceleration energy of 30 keV and with a dose of 5.times.10.sup.15 cm.sup.-2. The purpose of this ion implantation is to prevent the lowering of the phosphorus concentration in the silicon film. That is, the phosphorus in the silicon film of the layered polycide structure in which the phosphorus doped silicon film and the tungsten silicide film are stacked is diffused into the tungsten silicide film resulting in extremely lowering the phosphorus concentration in the silicon film containing the phosphorus. In an attempt to overcome this problem, the phosphorus is ion-implanted with such an energy that allows the phosphorus to reach the interface between the silicon film containing the phosphorus and the tungsten silicide so that a sufficient amount of phosphorus is added in advance into the tungsten film.
As shown in FIG. 1B, the tungsten silicide film 5 and the silicon film 4 are selectively and sequentially etched whereby a gate electrode is formed.
Next, as shown in FIG. 1C, by using the gate electrode and the field oxide film 2 as masks, a diffusion layer 7 is formed by impurity ion-implantation in a surface portion of the silicon substrate 1 at the element formation region, and an interlayer insulating film 8 of 0.8 .mu.m thick is deposited by a CVD process on a surface including that of the gate electrode. Then, the interlayer insulating film 8 is selectively anisotropically etched whereby a contact hole 11 is formed.
Thereafter, as shown in FIG. 1D, on a surface of the interlayer insulating film 8 including a surface of the contact hole 11, a phosphorus doped silicon film 12 of 0.1 .mu.m thick and a tungsten silicide film 13 of 0.2 .mu.m thick are sequentially deposited and stacked and, on the entire surface, phosphorus ions are implanted at an acceleration energy of 50 keV and with a dose of 5.times.10.sup.16 cm.sup.-2 and, thereafter, the tungsten silicide film 13 and the silicon film 12 are selectively sequentially etched thereby forming bit lines in the polycide structure.
In the prior art method for fabricating the semiconductor device explained above, in order to prevent the lowering of the conductivity caused by the diffusion, into the silicide film, of the impurity in the silicon film of the electrodes or interconnects in the polycide structure, the impurity is ion-implanted near the interface between the silicon film and silicide film. However, a problem is associated with the polycide structure in which films are formed thin in order to minimize the step formation. The silicon film containing the impurity and disposed under the silicide film tends to become thinner than the silicide film, the impurity ions, although intended to be implanted to near the interface, spread through to the gate insulating film due to implantation energy variations, or due to the breakdown voltage of the gate insulation being lowered as a result of the charge up effect caused by the ion charges.
A further problem is that, since the reflectivity to the exposure wavelength of the silicide film is large so as to cause halation to occur, a pattern precision during the lithography process is lowered leading, in a worst case, to the occurrence of electrical shorts among interconnects.